SH7713 datasheet(891/904 Pages) RENESAS

891 / 904 page

Appendix

Rev.1.50 Aug. 30, 2006 Page 851 of 860

REJ09B0288-0150

Reset

Power-Down States

Pin Name

I/O

Power-on

Reset

Manual

Reset

Software

Standby

Sleep

Release of

Bus

Mastership

Handling of

Unused Pins

VssQ-RTC



VssQ

Vcc-PLL1



Vcc*

Vss-PLL1



Vss*

Vcc-PLL2



Vcc*

Vss-PLL2



Vss*

[Legend]

Input state

Input state (however, input is fixed by the internal logic)

Output state (undefined although the level is high or low)

Low-level output

High-level output

High impedance (input or output buffer off)

Input/output buffer off, pull-up on

Input buffer on, output buffer off, pull-up on

Output buffer on or input buffer off (pull-up on or off), depending on register settings

Input or output depending on register settings

Notes:

1. Depends on clock mode.

2. The state is P when the port function is used.

3. The state is K when the port function is used.

4. The state is Z or H depending on register settings.

5. The state is Z or O depending on register settings.

6. The status is Z when the function select bit is set as reserved in the PETCR register in

the PFC module.

7. To avoid the power friction, Vcc-PLL1, Vcc-PLL2, Vss-PLL1, Vss-PLL2, and other Vcc

and Vss should be wired in three independent patterns from the board power-supply

source.

8. When power-on reset is executed, reserved condition is selected. Therefore, rewriting

by setting PETCR register in PFC module is mandatory.

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