SH7713 datasheet(171/904 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 131 of 860

REJ09B0288-0150

Logical Shift: Figure 3.18 shows the logical shift operation flow.

32 31

16 15

32 31

16 15

Shift out

Cleared to 0

Ignored

Left shift

Right shift

32 31

22 21 16

Imm2

Shift amount data

(source 2)

> = 0

< 0

+16- -16

DSR

Updated

Figure 3.18 Logical Shift Operation Flow

As shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand

and the destination operand. The lower word and guard-bit parts are ignored for the source

operand and those of the destination operand are automatically cleared as in the ALU logical

operations. The shift amount is specified by the source 2 operand as an integer data. The source 2

operand can be specified by either the register or immediate operand. The available shift range is

from –16 to +16. Here, a negative value means the right shift, and a positive value means the left

shift. It is possible for any source 2 operand to specify from –32 to +31, but the result is unknown

if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the

source 1 operand must be the same register as the destination's. These operations are executed in

the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which

memory access is performed.

Every time a logical shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically

updated in accordance with the operation result. In case of a conditional operation, they are not

updated even though the specified condition is true and the operation is executed. In case of an

unconditional operation, they are always updated in accordance with the operation result. The

definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit

result is:

1. Carry or Borrow Mode: CS[2:0] = 000

The DC bit indicates the last shifted out data as the operation result.

2. Negative Value Mode: CS[2:0] = 001

Bit 31 of the operation result is loaded into the DC bit.

3. Zero Value Mode: CS[2:0] = 010

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