SH7721 datasheet(367/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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367 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 305 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

5 to 2



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

HW1

HW0

R/W

Number of Delay Cycles from

RD, WEn (BEn) negation to

Address,

CSn negation

Specify the number of delay cycles from

RD and WEn

(

BEn) negation to address and CSn negation.

00: 0.5 cycle

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

• CS5AWCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 19



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

WW2

WW1

WW0

R/W

Number of Write Access Wait Cycles

Specify the number of cycles that are necessary for write

access.

000: The same cycles as WR3 to WR0 setting (read or

write access wait)

001: 0 cycles

010: 1 cycle

011: 2 cycles

100: 3 cycles

101: 4 cycles

110: 5 cycles

111: 6 cycles

15 to 13



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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