SH7721 datasheet(365/1524 Pages) RENESAS

365 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 303 of 1458

REJ09B0033-0300

• CS4WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BAS

R/W

Byte Access Selection for Byte-Selection SRAM

Specifies the

WEn (BEn) and RD/WR signal timing when

the byte-selection SRAM interface is used.

0: Asserts the

WEn (BEn) signal at the read/write timing

and asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn (BEn) signal during the read/write

access cycle and asserts the RD/

WR signal at the write

timing.



Reserved

This bit is always read as 0. The write value should always

be 0.

WW2

WW1

WW0

R/W

Number of Write Access Wait Cycles

Specify the number of cycles that are necessary for write

access.

000: The same cycles as WR3 to WR0 setting (read or

write access wait)

001: 0 cycles

010: 1 cycle

011: 2 cycles

100: 3 cycles

101: 4 cycles

110: 5 cycles

111: 6 cycles

15 to 13



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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