SH7721 datasheet(373/1524 Pages) RENESAS

373 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 311 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

5 to 2



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

HW1

HW0

R/W

Number of Delay Cycles from

RD, WEn (BEn) negation to

Address,

CSn negation

Specify the number of delay cycles from

RD and WEn

(

BEn) negation to address and CSn negation.

00: 0.5 cycle

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

(2)

Burst ROM (Clock Asynchronous)

• CS0WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BEN

R/W

Burst Enable Specification

Enables or disables 8-burst access for a 16-bit bus width or

16-burst access for an 8-bit bus width during 16-byte access.

If this bit is set to 1, 2-burst access is performed four times

when the bus width is 16 bits and 4-burst access is

performed four times when the bus width is 8 bits.

To use a device that does not support 8-burst access or 16-

burst access, set this bit to 1.

0: Enables 8-burst access for a 16-bit bus width and 16-burst

access for an 8-bit bus width.

1: Disables 8-burst access for a 16-bit bus width and 16-burst

access for an 8-bit bus width.

19, 18



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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