SH7721 datasheet(374/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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374 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 312 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

BW1

BW0

R/W

Number of Burst Wait Cycles

Specify the number of wait cycles to be inserted between

the second or later access cycles in burst access.

00: 0 cycles

01: 1 cycle

10: 2 cycles

11: 3 cycles

15 to 11



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

Number of Access Wait Cycles

Specify the number of wait cycles to be inserted in the first

access cycle.

0000: 0 cycles

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

SH7721 Datasheet(PDF) 374 Page - Renesas Technology Corp

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