SH7721 datasheet(378/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

378 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 316 of 1458

REJ09B0033-0300

(3)

SDRAM

• CS2WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 9



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

A2CL1

A2CL0

R/W

CAS Latency for Area 2

Specify the CAS latency for area 2.

00: 1 cycle

01: 2 cycles

10: 3 cycles

11: 4 cycles

6 to 0



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

• CS3WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 15



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

TRP1

TRP0

R/W

Number of Cycles from Auto-Precharge/PRE Command to

ACTV Command

Specify the number of minimum cycles from the start of auto-

precharge or issuing of PRE command to the issuing of

ACTV command for the same bank. The setting for areas 2

and 3 is common.

00: 1 cycle

01: 2 cycles

10: 3 cycles

11: 4 cycles



Reserved

This bit is always read as 0. The write value should always be

SH7721 Datasheet(PDF) 378 Page - Renesas Technology Corp

SH7721 Datasheet(HTML) 378 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL