SH7721 datasheet(379/1524 Pages) RENESAS

379 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 317 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

TRCD1

TRCD0

R/W

Number of Cycles from ACTV Command to

READ(A)/WRIT(A) Command

Specify the number of minimum cycles from issuing ACTV

command to issuing READ(A)/WRIT(A) command. The

setting for areas 2 and 3 is common.

00: 1 cycle

01: 2 cycles

10: 3 cycles

11: 4 cycles



Reserved

This bit is always read as 0. The write value should always

be 0.

A3CL1

A3CL0

R/W

CAS Latency for Area 3.

Specify the CAS latency for area 3.

00: 1 cycle

01: 2 cycles

10: 3 cycles

11: 4 cycles

When connecting the SDRAM to area 2 and area 3, set

the CAS latency to the bits 8 and 7 in the CS2WCR

mode setting. (See table 9.19.)

6, 5



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

TRWL1

TRWL0

R/W

Number of Cycles from WRITA/WRIT Command to Auto-

Precharge/PRE Command

Specifies the number of cycles from issuing WRITA/WRIT

command to the start of auto-precharge or to issuing PRE

command. The setting for areas 2 and 3 is common.

00: 0 cycles

01: 1 cycle

10: 2 cycles

11: 3 cycles

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