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SH7721 Datasheet(PDF) 383 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 383 Page - Renesas Technology Corp |
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383 / 1524 page  Section 9 Bus State Controller (BSC) Rev. 3.00 Jan. 18, 2008 Page 321 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 10 9 8 7 PCW3 PCW2 PCW1 PCW0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 5, 4 All 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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