SH7721 datasheet(387/1524 Pages) RENESAS

387 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 325 of 1458

REJ09B0033-0300

9.4.4

SDRAM Control Register (SDCR)

SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be

connected.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

A2ROW1

A2ROW0

R/W

Number of Bits of Row Address for Area 2

Specify the number of bits of row address for area 2.

00: 11 bits

01: 12 bits

10: 13 bits

11: Reserved (setting prohibited)



Reserved

This bit is always read as 0. The write value should always

be 0.

A2COL1

A2COL0

R/W

Number of Bits of Column Address for Area 2

Specify the number of bits of column address for area 2.

00: 8 bits

01: 9 bits

10: 10 bits

11: Reserved (setting prohibited)

15, 14



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

DEEP

R/W

Deep Power-Down Mode

This bit is valid for low-power SDRAM. If the RMODE bit is

set to 1 while this bit is set to 1, the deep power-down entry

command is issued and the low-power SDRAM enters the

deep power-down mode.

0: Self-refresh mode

1: Deep power-down mode

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