SH7721 datasheet(390/1524 Pages) RENESAS

390 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 328 of 1458

REJ09B0033-0300

9.4.5

Refresh Timer Control/Status Register (RTCSR)

RTCSR specifies various items about refresh for SDRAM.

When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write

protection.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 8



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CMF

R/W

Compare Match Flag

Indicates that a compare match occurs between the refresh

timer counter (RTCNT) and refresh time constant register

(RTCOR). This bit is set or cleared in the following

conditions.

0: Clearing condition: When 0 is written in CMF after reading

out RTCSR during CMF = 1.

1: Setting condition: When the condition RTCNT = RTCOR is

satisfied.

CMIE

R/W

Compare Match Interrupt Enable

Enables or disables a CMF interrupt request when the CMF

bit of RTCSR is set to 1.

0: Disables the CMF interrupt request

1: Enables the CMF interrupt request

CKS2

CKS1

CKS0

R/W

Clock Select

Select the clock input to count-up the refresh timer counter

(RTCNT).

000: Stop the counting-up

001: B

φ/4

010: B

φ/16

011: B

φ/64

100: B

φ/256

101: B

φ/1024

110: B

φ/2048

111: B

φ/4096

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