SH7721 datasheet(392/1524 Pages) RENESAS

392 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 330 of 1458

REJ09B0033-0300

9.4.7

Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1

and RTCNT is cleared to 0.

When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.

This request is maintained until the refresh operation is performed. If the request is not processed

when the next matching occurs, the previous request is ignored.

If the CMIE bit of the RTCSR is set to 1, an interrupt is requested by this matching signal. This

request is maintained until the CMF bit in RTCSR is cleared to 0. Clearing the CMF bit in RTCSR

affects only interrupts and does not affect refresh requests. This makes it possible to count the

number of refresh requests during refresh by interrupts, and to specify the refresh and interval

timer interrupts simultaneously. When the RTCOR is written, the upper 16 bits of the write data

must be H'A55A to cancel write protection.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 8



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

7 to 0



All 0

R/W

8-bit Counter

9.4.8

SDRAM Mode Registers 2, 3 (SDMR2 and SRMR3)

For the settings of SDRAM mode registers (SDMR2 and SDMR3), see table 9.19.

SH7721 Datasheet(PDF) 392 Page - Renesas Technology Corp