SH7721 datasheet(389/1524 Pages) RENESAS

389 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 327 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

BACTV

R/W

Bank Active Mode

Specifies to access whether in auto-precharge mode (using

READA and WRITA commands) or in bank active mode

(using READ and WRIT commands).

0: Auto-precharge mode (using READA and WRITA

commands)

1: Bank active mode (using READ and WRIT commands)

Note: Bank active mode can be used only in area 3. In this

case, the bus width can be selected as 16 or 32 bits.

When both areas 2 and 3 are set to SDRAM, specify

auto-precharge mode.

7 to 5



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

A3ROW1

A3ROW0

R/W

Number of Bits of Row Address for Area 3

Specify the number of bits of the row address for area 3.

00: 11 bits

01: 12 bits

10: 13 bits

11: Reserved (setting prohibited)



Reserved

This bit is always read as 0. The write value should always

be 0.

A3COL1

A3COL0

R/W

Number of Bits of Column Address for Area 3

Specify the number of bits of the column address for area 3.

00: 8 bits

01: 9 bits

10: 10 bits

11: Reserved (setting prohibited)

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