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SH7721 Datasheet(PDF) 384 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 384 Page - Renesas Technology Corp |
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384 / 1524 page ![]() Section 9 Bus State Controller (BSC) Rev. 3.00 Jan. 18, 2008 Page 322 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 3 2 1 0 TEH3 TEH2 TEH1 TEH0 0 0 0 0 R/W R/W R/W R/W Delay from RD or WE Negate to Address Specify the address hold time from RD or WE negate in the PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles |
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