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SH7721 Datasheet(PDF) 399 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 399 Page - Renesas Technology Corp

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Section 9
Bus State Controller (BSC)
Rev. 3.00 Jan. 18, 2008 Page 337 of 1458
REJ09B0033-0300
9.5.2
Normal Space Interface
(1)
Basic Timing
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 9.5.7, Byte-Selection SRAM Interface. Figure 9.3 shows the basic timings of normal space
access. A no-wait normal access is completed in two cycles. The
BS signal is asserted for one
cycle to indicate the start of a bus cycle.
CKIO
Note: * The waveform for DACKn is when active low is specified.
A
RD/
WR
RD/
WR
D
DACKn
CSn
T1
T2
RD
WEn(BEn)
BS
D
Read
Write
*
Figure 9.3
Normal Space Basic Access Timing (Access Wait 0)



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