SH7721 datasheet(400/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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400 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 338 of 1458

REJ09B0033-0300

There is no access size specification when reading. The correct access start address is output in the

least significant bit of the address, but since there is no access size specification, 32 bits are always

read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the

WEn

(

BEn) signal for the byte to be written is asserted.

It is necessary to output the data that has been read using

RD when a buffer is established in the

data bus. The RD/

WR signal is in a read state (high output) when no access has been carried out.

Therefore, care must be taken when controlling the external data buffer, to avoid collision.

Figures 9.4 and 9.5 show the basic timings of normal space accesses. If the WM bit of the

CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.4). If the

WM bit of the CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted

(figure 9.5).

SH7721 Datasheet(PDF) 400 Page - Renesas Technology Corp