SH7721 datasheet(405/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 343 of 1458

REJ09B0033-0300

9.5.3

Access Wait Control

Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to

WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in

read access and in write access. The areas other than 4, 5A, and 5B have common access wait for

read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a

normal space access shown in figure 9.9.

CKIO

A25 to A0

CSn

RD/

D31 to D0

WEn(BEn)

Read

Write

DACKn*

Note: * The waveform for DACKn is when active low is specified.

Figure 9.9

Wait Timing for Normal Space Access (Software Wait Only)

When the WM bit in CSnWCR is cleared to 0, the external wait input

WAIT signal is also

sampled.

WAIT pin sampling is shown in figure 9.10. A 2-cycle wait is specified as a software

wait. The

WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw

cycle to the T2 cycle.

SH7721 Datasheet(PDF) 405 Page - Renesas Technology Corp