SH7721 datasheet(607/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 545 of 1458

REJ09B0033-0300

15.5

Usage Notes

Note that the kinds of operation and contention described below can occur during TPU operation.

(1)

Input Clock Restrictions

The input clock pulse width must be at least 2 states in the case of single-edge detection, and at

least 3 states in the case of both-edge detection. The TPU will not operate properly with a

narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 2 states, and the pulse width must be at least 3 states. Figure 15.19 shows the input clock

conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TPU_TCLKA

(TPU_TCLKC)

TPU_TCLKB

(TPU_TCLKD)

Pulse width

Notes: Phase difference and overlap

Pulse width

: 2 states or more

: 3 states or more

Figure 15.19

Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

SH7721 Datasheet(PDF) 607 Page - Renesas Technology Corp