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SH7721 Datasheet(PDF) 609 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 609 Page - Renesas Technology Corp |
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609 / 1524 page ![]() Section 16 Compare Match Timer (CMT) TIMCMT1A_000020011000 Rev. 3.00 Jan. 18, 2008 Page 547 of 1458 REJ09B0033-0300 Section 16 Compare Match Timer (CMT) This LSI includes a 32-bit compare match timer (CMT) of five channels (channel 0 to channel 4). 16.1 Features • 16 bits/32 bits can be selected. • Each channel is provided with an auto-reload up counter. • All channels are provided with 32-bit constant registers and 32-bit up counters that can be written or read at any time. • Allows selection among three counter input clocks for channel 0 to channel 4: Peripheral clock (Pφ): 1/8, 1/32, and 1/128 • One-shot operation and free-running operation are selectable. • Allows selection of compare match or overflow for the interrupt source. • Generate a DMA transfer request when compare match or overflow occurs in channels 0 to 4. • Module standby mode can be set. |
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