SH7721 datasheet(613/1524 Pages) RENESAS

613 / 1524 page

Section 16 Compare Match Timer (CMT)

Rev. 3.00 Jan. 18, 2008 Page 551 of 1458

REJ09B0033-0300

16.2.2

Compare Match Timer Control/Status Register (CMCSR)

CMCSR is a 16-bit register that indicates the occurrence of compare matches, enables interrupts

and DMA transfer request, and sets the counter input clocks.

Do not change bits other than bits CMF and OVF during the compare match timer counter

(CMCNT) operation.

Bit

Bit Name

Initial

Value

R/W

Description

CMF

R/(W)*

Compare Match Flag

This flag indicates whether or not values of the compare

match timer counter (CMCNT) and compare match timer

constant register (CMCOR) have matched.

Software cannot write 1 to the bit. When one-shot is

selected for the counter operation, counting resumes by

clearing this bit.

0: CMCNT and CMCOR values have not matched

[Clearing condition]

• Write 0 to CMF after reading CMF=1

1: CMCNT and CMCOR values have matched

OVF

R/(W)*

Overflow Flag

This flag indicates whether or not the compare match

timer counter (CMCNT) has overflowed and been cleared

to 0. Software cannot write 1 to this bit.

0: CMCNT has not overflowed

[Clearing condition]

• Write 0 to OVF after reading OVF=1

1: CMCNT has overflowed

13 to 10



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SH7721 Datasheet(PDF) 613 Page - Renesas Technology Corp

SH7721 Datasheet(HTML) 613 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL