SH7721 datasheet(614/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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614 / 1524 page

Section 16 Compare Match Timer (CMT)

Rev. 3.00 Jan. 18, 2008 Page 552 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

CMS

R/W

Compare Match Timer Counter Size

Selects whether the compare match timer counter

(CMCNT) is used as a 16-bit counter or a 32-bit counter.

This setting becomes the valid size for the compare

match timer constant register (CMCOR).

0: Operates as a 32-bit counter

1: Operates as a 16-bit counter

CMM

R/W

Compare Match Mode

Selects one-shot operation or free-running operation of

the counter.

0: One-shot operation

1: Free-running operation

7, 6

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CMR1

CMR0

R/W

Compare Match Request 1, 0

Selects enable or disable for a DMA transfer request or

internal interrupt request in a compare match.

00: Disables a DMA transfer request and internal

interrupt request

01: Enables DMA transfer request

10: Enables an internal interrupt request

11: Setting prohibited

—

Reserved

This bit is always read as 0. The write value should

always be 0.

SH7721 Datasheet(PDF) 614 Page - Renesas Technology Corp

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