SH7721 datasheet(616/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 16 Compare Match Timer (CMT)

Rev. 3.00 Jan. 18, 2008 Page 554 of 1458

REJ09B0033-0300

16.3

Operation

16.3.1

Counter Operation

The CMT starts the operation of the counter by writing a 1 to the STRn bit in CMSTR of a

channel that has been selected for operation. Complete all of the settings before starting the

operation. Do not change the register settings other than by clearing flag bits.

The counter operates in one of two ways.

• One-Shot Operation

One-shot operation is selected by setting the CMM bit in CMCSR to 0. When the value in

CMCNT matches the value in CMCOR, the value in CMCNT is cleared to H'00000000 and

the CMF bit in CMCSR is set to 1. Counting by CMCNT stops after it has been cleared.

To detect an overflow interrupt, set the value in CMCOR to H'FFFFFFFF. When the value in

CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and bits CMF and

OVF in CMCSR are set to 1.

Value in

CMCNT

CMCOR

CMF = 1

OVF = 1 (When an overflow is detected)

H'00000000

Time

Figure 16.2 Counter Operation (One-Shot Operation)

SH7721 Datasheet(PDF) 616 Page - Renesas Technology Corp