SH7721 datasheet(617/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

617 / 1524 page

Section 16 Compare Match Timer (CMT)

Rev. 3.00 Jan. 18, 2008 Page 555 of 1458

REJ09B0033-0300

• Free-Running Operation

Free-running operation is selected by setting the CMM bit in CMCSR to 1. When the value in

CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and the CMF bit in

CMCSR is set to 1. CMCNT resumes counting-up after it has been cleared.

To detect an overflow interrupt, set CMCOR to H'FFFFFFFF. When the values in CMCNT

and CMCOR match, CMCNT is cleared to H'00000000 and bits CMF and OVF in CMCSR

are set to 1.

CMCOR

H'00000000

Value in

CMCNT

CMF=1

OVF=1 (When an overflow is detected)

Time

Figure 16.3 Counter Operation (Free-Running Operation)

16.3.2

Counter Size

In this module, the size of the counter is selectable as either 16 or 32 bits. This is selected by the

CMS bit in CMCSR.

When the 16-bit size is selected, use a 32-bit value which has H'0000 as its upper half to set

CMCOR.

To detect an overflow interrupt, the value must be set to H'0000FFFF.

SH7721 Datasheet(PDF) 617 Page - Renesas Technology Corp