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SH7721 Datasheet(PDF) 619 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 619 Page - Renesas Technology Corp

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Section 16 Compare Match Timer (CMT)
Rev. 3.00 Jan. 18, 2008 Page 557 of 1458
REJ09B0033-0300
16.3.5
Compare Match Flag Set Timing (All Channels)
The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and
CMCNT match. The compare match signal is generated upon the final state of the match (timing
at which the CMCNT value is updated to H'0000). Consequently, after CMCOR and CMCNT
match, a compare match signal will not be generated until a CMCNT counter clock is input.
Figure 16.4 shows the set timing of the CMF bit.
Peripheral operating
clock (P
φ)
Counter clock
CMCNT
CMCOR
Compare match signal
and interrupt signal
N + 1
clock
N
0
N
Figure 16.4 CMF Set Timing



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