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SH7721 Datasheet(PDF) 139 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 139 Page - Renesas Technology Corp

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Section 2
CPU
Rev. 3.00 Jan. 18, 2008 Page 77 of 1458
REJ09B0033-0300
1. Number of states before the chip enters the sleep state.
2. For details, refer to section 7, Exception Handling.
2.6.2
Operation Code Map
Table 2.12 shows the operation code map.
Table 2.12
Operation Code Map
Instruction Code
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MSB
LSB
MD: 00
MD: 01
MD: 10
MD: 11
0000
Rn
Fx
0000
0000
Rn
Fx
0001
0000
Rn
00MD
0010
STC
SR, Rn
STC
GBR, Rn
STC
VBR, Rn
STC
SSR, Rn
0000
Rn
01MD
0010
STC
SPC, Rn
0000
Rn
10MD
0010
STC
R0_BANK, Rn
STC
R1_BANK, Rn
STC
R2_BANK, Rn
STC
R3_BANK, Rn
0000
Rn
11MD
0010
STC
R4_BANK, Rn
STC
R5_BANK, Rn
STC
R6_BANK, Rn
STC
R7_BANK, Rn
0000
Rm
00MD
0011
BSRF
Rm
BRA
Rm
0000
Rm
10MD
0011
PREF
@Rm
0000
Rn
Rm
01MD
MOV.B
Rm, @(R0, Rn)
MOV.W
Rm, @(R0, Rn)
MOV.L
Rm,@(R0, Rn)
MUL.L
Rm, Rn
0000
0000
00MD
1000
CLRT
SETT
CLRMAC
LDTLB
0000
0000
01MD
1000
CLRS
SETS
0000
0000
Fx
1001
NOP
DIV0U
0000
0000
Fx
1010
0000
0000
Fx
1011
RTS
SLEEP
RTE
0000
Rn
Fx
1000
0000
Rn
Fx
1001
MOVT
Rn
0000
Rn
Fx
1010
STS
MACH, Rn
STS
MACL, Rn
STS
PR, Rn
0000
Rn
Fx
1011
0000
Rn
Rm
11MD
MOV. B
@(R0, Rm), Rn
MOV.W
@(R0, Rm), Rn
MOV.L
@(R0, Rm), Rn
MAC.L
@Rm+,@Rn+
0001
Rn
Rm
disp
MOV.L
Rm, @(disp:4, Rn)
0010
Rn
Rm
00MD
MOV.B
Rm, @Rn
MOV.W
Rm, @Rn
MOV.L
Rm, @Rn
0010
Rn
Rm
01MD
MOV.B
Rm, @–Rn
MOV.W
Rm, @–Rn
MOV.L
Rm, @–Rn
DIV0S
Rm, Rn
0010
Rn
Rm
10MD
TST
Rm, Rn
AND
Rm, Rn
XOR
Rm, Rn
OR
Rm, Rn



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