SH7721 datasheet(228/1524 Pages) RENESAS

228 / 1524 page

Section 4 Memory Management Unit (MMU)

Rev. 3.00 Jan. 18, 2008 Page 166 of 1458

REJ09B0033-0300

Although the functions of the MMU could also be implemented by software alone, the need for

translation to be performed by software each time a process accesses physical memory would

result in poor efficiency. For this reason, a buffer for address translation (translation look-aside

buffer: TLB) is provided in hardware to hold frequently used address translation information. The

TLB can be described as a cache for storing address translation information. Unlike cache

memory, however, if address translation fails, that is, if an exception is generated, switching of

address translation information is normally performed by software. This makes it possible for

memory management to be performed flexibly by software.

The MMU has two methods of mapping from virtual memory to physical memory: a paging

method using fixed-length address translation, and a segment method using variable-length

address translation. With the paging method, the unit of translation is a fixed-size address space

(usually of 1 to 64 kbytes) called a page.

In the following text, the address space in virtual memory is referred to as virtual address space,

and address space in physical memory as physical memory space.

SH7721 Datasheet(PDF) 228 Page - Renesas Technology Corp