SH7760 datasheet(55/1345 Pages) RENESAS

55 / 1345 page

Rev. 1.0, 02/03, page 5 of 1294

Item

Features

Cache memory

• Instruction cache (IC)

 16-kbyte, 2-way set associative (LRU)

 256 entries, 32-byte block length

 Cache-double-mode (16-kbyte cache)

 Index mode

• Operand cache (OC)

 32-kbyte, 2-way set associative (LRU)

 512 entries, 32-byte block length

 Cache-double-mode (32-kbyte cache)

 Index mode

 RAM mode (16-kbyte cache + 16-kbyte RAM)

 Choice of write method (copy-back or write-through)

• Single-stage copy-back buffer, single-stage write-through buffer

• Cache memory contents can be accessed directly by address mapping

(usable as on-chip memory)

• Store queue (32 bytes × 2 entries)

Interrupt controller

(INTC)

• Nine independent external interrupts: NMI, IRL3 to IRL0, and IRQ7 to

IRQ4

• 15-level signed external interrupts: IRL3 to IRL0

• On-chip peripheral module interrupts: Priority level can be set for each

module

User break

controller (UBC)

• Supports debugging by means of user break interrupts

• Two break channels

• Address, data value, access type, and data size can all be set as break

conditions

• Supports sequential break function

SH7760 Datasheet(PDF) 55 Page - Renesas Technology Corp