SH7760 datasheet(97/1345 Pages) RENESAS

97 / 1345 page

Rev. 1.0, 02/03, page 47 of 1294

3.3.2

Floating-Point Status/Control Register (FPSCR)

FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and

selects the rounding mode. Do not set the SZ and PR bits to 1 simultaneously; this setting is

reserved.

Bit:

0000000000000100

0000000001

Initial value:

R/W

Enable

Flag

Cause

RM1

RM0

Cause

R/W

R/W:

Bit:

Initial value:

R/W:

9876543210

R/W

Bit

Bit Name

Initial Value

R/W

Description

31 to 22 —

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

Floating-Point Register Bank

0: FPR0_BANK0 to FPR15_BANK0 are assigned to

FR0 to FR15 and FPR0_BANK1 to

FPR15_BANK1 are assigned to XF0 to XF15

1: FPR0_BANK0 to FPR15_BANK0 are assigned to

XF0 to XF15 and FPR0_BANK1 to

FPR15_BANK1 are assigned to FR0 to FR15

R/W

Transfer Size Mode

0: Data size of FMOV instruction is 32-bits

1: Data size of FMOV instruction is a 32-bit register

pair (64 bits)

R/W

Precision Mode

0: Floating-point instructions are executed as

single-precision operations

1: Floating-point instructions are executed as

double-precision operations (graphics support

instructions are undefined)

R/W

Denormalization Mode

0: Denormalized number is treated as such

1: Denormalized number is treated as zero

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