SH7760 datasheet(32/1345 Pages) RENESAS

32 / 1345 page

Rev. 1.0, 02/03, page xxx of xlviii

Figure 10.52 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait,

32-Bit Bus Width, 64-Bit Data Transfer) ..............................................................348

Figure 10.53 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0,

One External Wait Inserted, 32-Bit Bus Width, 64-Bit Data Transfer).................349

Figure 10.54 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait,

32-Bit Bus Width, 64-Bit Data Transfer) ..............................................................350

Figure 10.55 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1,

One External Wait Inserted, 32-Bit Bus Width, 64-Bit Data Transfer)................351

Figure 10.56 Example of 32-Bit Data Width Byte Control SRAM

352

Figure 10.57 Byte Control SRAM Basic Read Cycle (No Wait)................................................353

Figure 10.58 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ......................354

Figure 10.59 Byte Control SRAM Basic Read Cycle

(One Internal Wait + One External Wait)..............................................................355

Figure 10.60 Wait Cycles between Access Cycles .....................................................................357

Figure 10.61 Arbitration Sequence .............................................................................................359

Section 11 Direct Memory Access Controller (DMAC)

Figure 11.1 DMAC Block Diagram............................................................................................362

Figure 11.2 DMABRG Block Diagram ......................................................................................363

Figure 11.3 DMAC Transfer Flowchart .....................................................................................405

Figure 11.4 Round Robin Mode .................................................................................................409

Figure 11.5 Example of Changes in Priority Order in Round Robin Mode................................411

Figure 11.6 Data Flow in Single Address Mode.........................................................................412

Figure 11.7 DMA Transfer Timing in Single Address Mode .....................................................413

Figure 11.8 Operation in Dual Address Mode ............................................................................414

Figure 11.9 Example of Transfer Timing in Dual Address Mode ..............................................415

Figure 11.10 Example of DMA Transfer in Cycle Steal Mode ..................................................416

Figure 11.11 Example of DMA Transfer in Burst Mode............................................................416

Figure 11.12 Bus Handling with Two DMAC Channels Operating ...........................................420

Figure 11.13 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel Mode

External Bus

→ External Bus/DREQ (Level Detection), DACK (Read Cycle)....423

Figure 11.14 Dual Address Mode/Cycle Steal Mode in DMABRG Mode

External Bus

→ External Bus/DREQ (Level Detection), DACK (Read Cycle)....424

Figure 11.15 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel

Mode External Bus

→ External Bus/DREQ (Edge Detection),

DACK (Read Cycle)..............................................................................................425

Figure 11.16 Dual Address Mode/Cycle Steal Mode in DMABRG Mode

External Bus

→ External Bus/DREQ (Edge Detection), DACK (Read Cycle) ....426

Figure 11.17 Dual Address Mode/Burst Mode in External Request 2-Channel Mode

External Bus

→ External Device/DREQ (Level Detection),

DACK (Read Cycle)..............................................................................................427

Figure 11.18 Dual Address Mode/Burst Modes in DMABRG Mode

External Bus

→ External Bus/ DREQ (Level Detection), DACK (Read Cycle)...428

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