7733 datasheet(409/940 Pages) RENESAS

409 / 940 page

APPLICATIONS

7733 Group User’s Manual

17–2

Some application examples are described below.

Applications shown here are just examples. Modify the desired application to suit the user’s need and make

sufficient evaluation before actually using it.

17.1 Memory expansion

Memory • I/O expansion examples are described below.

• For functions and operations of pins used in memory • I/O expansion, refer to chapter “12. CONNECTING

EXTERNAL DEVICES.”

• For timing characteristics, refer to chapter “15. ELECTRICAL CHARACTERISTICS.”

• For timing characteristics and applications of the low voltage version, refer to chapter “18. LOW VOLTAGE

VERSION.”

17.1.1 Memory expansion model

Memory expansion to the external is enabled in the memory expansion or microprocessor mode. In the

7733 Group, the desired memory expansion model can be selected from four models listed in Table 17.1.1.

This selection depends on the level of the external data bus width selection signal (BYTE).

(1) Minimum model

The external data bus is 8 bits wide and the accessible area can be expanded up to 64 Kbytes.

No external address latch is necessary, so this model gives priority to cost and is most suitable when

connecting a memory of which data bus is 8 bits wide.

(2) Medium model A

The external data bus is 8 bits wide and the accessible area can be expanded up to 16 Mbytes.

The high-order 8 bits of the external address bus (A23 to A16) are multiplexed with the external data

bus. Therefore, one n-bit (n

≤ 8) address latch is necessary in order to latch n bits of address in A23

to A16.

(3) Medium model B

The external data bus is 16 bits wide and the accessible area can be expanded up to 64 Kbytes.

This model gives priority to speed. The middle-order 8 bits of the external address bus (A15 to A8) are

multiplexed with the external data bus. Therefore, one 8-bit address latch is necessary in order to latch

A15 to A8.

(4) Maximum model

The external data bus is 16 bits wide and the accessible area can be expanded up to 16 Mbytes.

The high- and middle- order 16 bits of the external address bus (A23 to A8) are multiplexed with the

external data bus. Therefore, both of the following latches are necessary:

• One 8-bit address latch used for latching A15 to A8

• One n-bit (n

≤ 8) address latch used for latching n bits of address in A23 to A16

17.1 Memory expansion

7733 Datasheet(PDF) 409 Page - Renesas Technology Corp