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7733 Datasheet(PDF) 446 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 446 Page - Renesas Technology Corp |
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446 / 940 page ![]() APPLICATIONS 7733 Group User’s Manual 17–39 (2) Initial settings for related registers Fig. 17.2.17 Initial settings for related registers 17.2 Serial I/O b7 b0 When the system clock (main clock) frequency = 16 MHz, transfer rate = 2 MHz. UART1 baud rate register (BRG1) (address 39 16) 0116 Transmission is enabled. b7 b0 UART1 transmit/receive control register 1 (address 3D 16) XX X Reception is disabled. XX 0 X 1 b7 b0 UART1 transmission interrupt control register (address 73 16) 0 00 UART1 transmission interrupt is disabled. X Pin P43:Output mode b7 b0 Port P4 direction register (address C 16) 1 Must be fixed to “0.” Clock synchronous serial I/O mode b7 b0 UART1 transmit/receive mode register (address 38 16) 0X X Internal clock is selected. X0 0 0 1 UART1 transmit/receive control register 0 (address 3C 16) CTS /RTS function is disabled. Pin TXD1’s output structure: CMOS output Transmit data is output at the falling edge of the transfer clock. LSB first BRG1 count source: f 2 b7 b0 0 01 0 !! 00 X: It may be “0” or “1.” Pin P43’s output level: “L” b7 b0 Port P4 register (address A 16) 0 |
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