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7733 Datasheet(PDF) 526 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 526 Page - Renesas Technology Corp |
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526 / 940 page  EXTERNAL ROM VERSION 7733 Group User’s Manual 20–10 Fig. 20.5.2 SFR area’s memory map UART 0 transmission interrupt control register UART 1 transmission interrupt control register INT2 /Key input interrupt control register Port P1 direction register (Note 3) UART 0 transmit/receive mode register UART 0 baud rate register (BRG0) UART 0 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 0 transmission buffer register UART 1 transmit/receive control register 0 UART 1 transmit/receive mode register UART 1 baud rate register (BRG1) UART 1 transmit/receive control register 1 UART 0 receive buffer register UART 1 transmission buffer register UART 1 receive buffer register Port P0 register (Note 3) A-D register 0 A-D register 2 Port P1 register (Note 3) Port P0 direction register (Note 3) Port P2 register (Note 3) Port P3 register (Note 3) Port P4 register (Note 3) Port P5 register Port P6 register Port P7 register Port P8 register A-D control register 0 A-D control register 1 A-D register 1 A-D register 3 A-D register 4 A-D register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001A 00001B 00001C 00001D 00001E 00001F 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002A 00002B 00002C 00002D 00002E 00002F 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003A 00003B 00003C 00003D 00003E 00003F 00000B 00000C 00000D 00000E 00000F 00000A 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F 00004B 00004C 00004D 00004E 00004F 00004A 000044 Address (Hexadecimal notation) Address (Hexadecimal notation) Timer A1 register Timer A4 register Timer A2 register Timer A3 register Timer B0 register Timer B1 register Timer B2 register Count start flag One-shot start flag Up-down flag Timer A0 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Watchdog timer register Watchdog timer frequency selection flag A-D/UART2 trans./rece. interrupt control register UART 0 receive interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register Processor mode register 1 Oscillation circuit control register 1 Serial transmit control register Port function control register Oscillation circuit control register 0 Timer A3 mode register Port P2 direction register (Note 3) Port P3 direction register (Note 3) Port P4 direction register (Note 3) Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Pulse output data register 1 (Note 1) A-D register 6 A-D register 7 UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Waveform output mode register (Note 1) Notes 1: Memory map of the M37733S4BFP differs from that of the M37733MHBXXXFP in addresses 1C16, 1D16, 6216, and 6316. 2: Writing to the reserved area is disabled. 3: These registers are used when outputting an arbitrary data in the stop or wait mode. Pulse output data register 0 (Note 1) Reserved area (Notes 1, 2) A-D control register 1 20.5 Memory allocation |
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