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7733 Datasheet(PDF) 530 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 530 Page - Renesas Technology Corp |
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530 / 940 page  EXTERNAL ROM VERSION 7733 Group User’s Manual 20–14 20.7 Timer A (2) Block description Figure 20.7.1 shows the block diagram for the pulse output mode. Figures 20.7.3 to 20.7.6 show the structures of registers related to the pulse output port mode. Also, Figure 20.7.2 shows the structure of the port P5 output control circuit. Fig. 20.7.1 Block diagram for pulse output port mode b3 b2 b1 b0 D Q D Q D Q D Q T D Q D Q D Q T Timer A0 D Q 45 Pulse width modulation selection bits (Bits 4, 5 at address 62 16) Pulse width modulation output by timer A3 Pulse width modulation output by timer A1 Timer A2 Pulse output data register 1 (Address 1C16) RTP13(P57/TA3IN) Polarity selection bit (Bit 3 at address 62 16) Pulse output data register 0 (Address 1D16) b3 b2 b1 b0 RTP12(P56/TA3OUT) RTP11(P55/TA2IN) RTP10(P54/TA2OUT) RTP03(P53/TA1IN) RTP01(P51/TA0IN) RTP02(P52/TA1OUT) RTP00(P50/TA0OUT) |
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