7477 datasheet(41/354 Pages) RENESAS

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HARDWARE

1.7 Central processing unit (CPU)

7470/7471/7477/7478 GROUP USER’S MANUAL

1-24

The CPU register states provided immediately after hardware reset are described below.

q The interrupt disable flag (I) of the Processor status register (PS) is set to “1.”

q The high-order 8 bits (PCH) of the Program counter (PC) become the contents of address FFFF16 and

the low-order 8 bits (PCL) become the contents of address FFFE16.

The contents of the other CPU registers are undefined, so be sure to initialize the CPU registers with

the program.

1.7.1 Accumulator (A)

The Accumulator is the central of microcomputer and is an 8-bit register. This accumulator is used for

arithmetic operations, data transfer, temporary storage, condition judgment, and is a general-purpose

1.7.2 Index register X (X), Index register Y (Y)

The Index register X and the Index register Y are 8-bit registers.

In the addressing mode using these Index registers, a value resulting from adding the contents of this

to a subroutine table or a memory table. The Index registers are provided with increment, decrement,

comparison and data transfer functions and can also be used as a simplified accumulator.

In the Index register X, when the index X mode flag (T) of the Processor status register is “1,” the contents

of the Index register become an operand address.

1.7.3 Stack pointer (S)

The Stack pointer is an 8-bit register which is used to call a subroutine or generate an interrupt.

For a branch from a routine being executed to a subroutine or an interrupt processing routine, it is

necessary to temporarily store (push) in memory the return address at the termination of this processing.

Usually, the internal RAM is used as the push destination, and this area is called a stack area. The stack

pointer indicates an address in the stack area to which the data will be pushed next.

Figure 1.7.2 shows a push operation to the stack area of the register and a pop operation from the Stack

area of the register.

The Program counter and registers other than the Processor status register are not automatically pushed.

Accordingly, be sure to push necessary registers with the program.

The PHA instruction and the PLA instruction are used for push and pop operations of the Accumulator and

the PHP instruction and the PLP instruction are used for push and pop operations of the Processor status

In the 7470/7471/7477/7478 group, the RAM in 0 page or 1 page is available as a stack area. Select it

by the stack page bit (bit 2) of the CPU mode register (address 00FB16), which will be described later (“0”

for 0 page or “1” for 1 page). In some products whose RAM capacity is 192 bytes or less, RAM does not

exist on 1 page, so be sure to set this bit to “0.”

The stack pointer is in an undefined state immediately after hardware reset. Be sure to initialize so as not

to destroy the data arranged in the RAM area.

7477 Datasheet(PDF) 41 Page - Renesas Technology Corp