7477 datasheet(72/354 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.11 Interrupts

1-55

Address

00FE16

00FF16

Timer 1

Timer 2

Timer 3

Timer 4

Serial I/O (7470/7471 group)

Serial I/O receive (7477/7478 group)

Serial I/O transmit (7477/7478 group)

A-D conversion

INT0

INT1

CNTR0/CNTR1

1.11.3 Interrupt control

Regarding interrupts other than the BRK instruction, the acceptance of them can be controlled by the

interrupt request bit, the interrupt enable bit and the interrupt disable flag. This section describes interrupt

control other than the BRK instruction.

Figure 1.11.6 shows a interrupt control diagram.

Interrupt source

Address

00FC16

00FD16

Bits

b6 (Note 1)

b5 (Note 2)

b6 (Note 2)

Bits

b6 (Note 1)

b5 (Note 2)

b6 (Note 2)

Interrupt request bits

Interrupt enable bits

Notes

1: This bit is not provided in the 7477/7478 group.

2: This bit is not provided in the 7470/7471 group.

Fig. 1.11.6 Interrupt control diagram

The interrupt request bit, the interrupt enable bit and the interrupt disable flag function independently and

do not affect one another. An interrupt is accepted when all the following conditions are satisfied.

q Interrupt request bit ............. “1”

q Interrupt enable bit .............. “1”

q Interrupt disable flag ............“0”

The priority is determined by hardware. However, a variety of priority processing can be executed by

software when the above flag and bits are used.

Table 1.11.2 shows a interrupt control bits for individual interrupt sources.

Table 1.11.2 Interrupt control bits for individual interrupt sources

Interrupt request bit

Interrupt enable bit

Interrupt disable flag

BRK instruction

Reset

Interrupt accepted

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