7477 datasheet(12/354 Pages) RENESAS

12 / 354 page

7470/7471/7477/7478 GROUP USER’S MANUAL

List of figures

CHAPTER 1. HARDWARE

Fig. 1.2.1 Memory expansion plan of 7470/7471/7477/7478 group ......................................... 1-4

Fig. 1.4.1 Pin configuration of 7470 group ................................................................................. 1-10

Fig. 1.4.2 Pin configuration of 7471 group ................................................................................. 1-11

Fig. 1.4.3 Pin configuration of 7477 group ................................................................................. 1-12

Fig. 1.4.4 Pin configuration of 7478 group ................................................................................. 1-13

Fig. 1.6.1 M37470Mx/Ex-XXXSP functional block diagram ..................................................... 1-17

Fig. 1.6.2 M37471Mx/Ex-XXXSP, M37471E8SS functional block diagram ........................... 1-18

Fig. 1.6.3 M37471Mx/Ex-XXXFP functional block diagram ..................................................... 1-19

Fig. 1.6.4 M37477Mx/E8-XXXSP/FP functional block diagram .................................................. 1-20

Fig. 1.6.5 M37478Mx/E8-XXXSP, M37478E8SS functional block diagram ........................................... 1-21

Fig. 1.6.6 M37478Mx/E8-XXXFP functional block diagram ..................................................... 1-22

Fig. 1.7.1 Structure of CPU registers .......................................................................................... 1-23

Fig. 1.7.2 Register push and pop at interrupt generation and subroutine call .................... 1-25

Fig. 1.8.1 Access area .................................................................................................................. 1-28

Fig. 1.9.1 Memory allocation of 7470/7471 group .................................................................... 1-31

Fig. 1.9.2 Memory allocation of 7477/7478 group .................................................................... 1-32

Fig. 1.9.3 Special function register (SFR) memory map ......................................................... 1-33

Fig. 1.9.4 Interrupt vector memory map ..................................................................................... 1-34

Fig. 1.10.1 I/O port writing and reading ..................................................................................... 1-36

Fig. 1.10.2 Structure of Port Pi direction register (i=0, 1, 2, 4) ............................................ 1-37

Fig. 1.10.3 Structure of Port P0 pull-up control register ......................................................... 1-38

Fig. 1.10.4 Structure of Ports P1 to P5 pull-up control register ............................................ 1-39

Fig. 1.10.5 Block diagram of Ports P0, P10 to P13 .................................................................................. 1-40

Fig. 1.10.6 Block diagram of Ports P14 to P17 (7470/7471 group) ....................................... 1-41

Fig. 1.10.7 Block diagram of Ports P14 to P17 (7477/7478 group) ....................................... 1-42

Fig. 1.10.8 Block diagram of Ports P2 to P4 ............................................................................ 1-43

Fig. 1.10.9 Block diagram of Port P5 ......................................................................................... 1-44

Fig. 1.11.1 Block diagram of interrupt input and key-on wake up circuit ............................. 1-50

Fig. 1.11.2 Interrupt operation ...................................................................................................... 1-52

Fig. 1.11.3 Changes of contents of Program counter and Stack pointer upon acceptance

of interrupt ................................................................................................................... 1-53

Fig. 1.11.4 Processing time up to the execution of interrupt processing routine ................ 1-54

Fig. 1.11.5 Timing after acceptance of interrupt ...................................................................... 1-54

Fig. 1.11.6 Interrupt control diagram ........................................................................................... 1-55

Fig. 1.11.7 Example of register setting ....................................................................................... 1-57

Fig. 1.11.8 Structure of Edge polarity selection register ......................................................... 1-59

Fig. 1.11.9 Structure of Interrupt request register 1 ................................................................ 1-60

Fig. 1.11.10 Structure of Interrupt request register 2 .............................................................. 1-60

7477 Datasheet(PDF) 12 Page - Renesas Technology Corp