7477 datasheet(88/354 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.12 Timers

[Setting method]

1 The count operation of a timer to be used is stopped.

Refer to “Table 1.12.2 Setting for count stop.”

2 Select a count source according to the event counter mode setting shown in Table1.12.9.

3 Set a count value in the timer.

Refer to “Table 1.12.7 Address allocation of timer.”

4 Start a count operation of timer to be used.

Refer to “Table 1.12.8 Count start setting.”

Table. 1.12.9 Event counter mode setting

Note: 0: The falling edge (An input, when it is inverted, becomes a count source).

1: The rising edge (An input itself becomes a count source).

–

Timer

to be

used

Timer 1

Timer 3

Timer 4

Edge polarity selection register

(EG: Address 00D416)

–

Select

(Note)

Select (Note)

–

Timer 12 mode register

(T12M: Address 00F816)

–

Timer 34 mode register

(T34M: Address 00F916)

–

Count

source

CNTR0

CNTR1

(3) Pulse output mode

The pulse output mode is a mode resulting from adding a pulse output operation to a timer mode

operation. In this mode, a pulse whose polarity is inverted at each overflow is output from the T0

(Timer 1 overflow signal/2) pin and the T1 (Timer 4 overflow signal/2) pin.

The operations in the pulse output mode are described below.

1 Start of count operation

After the count stop bit is set to “0,” a count operation starts. Each time a count source is input,

the contents of the timer are decremented by 1.

Note: Because the count stop bit is “0” immediately after reset release, the count operation is

automatically started immediately after reset release but no pulse is output.

2 Reload operation

When the timer overflows, the value resulting from decrementing 1 from the contents of the timer

latch is transferred (reloaded) to the timer.

3 Pulse is output

• A pulse whose polarity is inverted at each overflow is output from the T0 pin and the T1 pin.

• “H” or “L” can be selected as a level for a start of pulse output by each division flip-flop.

• A pulse output is started from the moment when the T0 or T1 pin output is selected by the Timer

12 mode register or the Timer 34 mode register.

4 Interrupt operation

2 Timer interrupt

When the timer overflows, an interrupt request occurs, so that the interrupt request bit is set.

The acceptance of interrupt is controlled by the interrupt enable bit of each timer.

5 Stop of count operation

When “1” is set in the counter stop bit by software, the count operation stops. (The count operation

continues until “1” is set in the count stop bit.)

Figure 1.12.5 shows a example of pulse output mode operation.

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