7477 datasheet(75/354 Pages) RENESAS

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HARDWARE

1.11 Interrupts

7470/7471/7477/7478 GROUP USER’S MANUAL

1-58

< Main routine >

In the main routine, set the INT edge polarity according to the INT pin input level just precedent

to execution of the STP/WIT instruction.

1 INT interrupt disable

2 q Select the falling edge when the INT pin input level is “H.”

q Select the rising edge when the INT pin input level is “L.”

3 Clear the INT interrupt request bit to “0” and enable an INT interrupt after one instruction

or more.

4 Clear the interrupt disable flag to “0.”

5 Execute the STP/WIT instruction

< INT interrupt processing routine >

In the INT interrupt processing routine, change the active edge of the INT interrupt without

performing release processing and proceed to the stop mode/wait mode in the case where the

stop mode/wait mode is released by detecting a falling edge.

q When the INT pin input level is “H” (when a rising edge is detected)

Processing for releasing the stop mode/wait mode

q When the INT pin input level is “L” (when a falling edge is detected)

[1] Select the rising edge

[2] Clear the INT interrupt request bit to “0”

[3] Pop from stack

[4] Perform

4 and 5 processing of the main routine.

2. An example of a countermeasure for the case where the stop mode/wait mode is released at the

rising edge of the INT0 pin input level or the falling edge of the INT1 pin input level after the same

signal is input to the INT0 pin and the INT1 pin.

Point: Select the INT interrupt, by the main routine, that becomes a source of release of the stop

mode/wait mode according to the INT pin input level just precedent to execution of the

STP/WIT instruction.

< Main routine >

1 INT0 and INT1 interrupt disable

2 Select the rising edge for the active edge of the INT0 interrupt.

Select the falling edge for the active edge of the INT1 interrupt.

3 q When the INT pin input level is “H”

Clear the INT1 interrupt request bit to “0” and enable the INT1 interrupt after one instruction

or more.

q When the INT pin input level is “L”

Clear the INT0 interrupt request bit to “0” and enable the INT0 interrupt after one instruction

or more.

4 Clear the interrupt disable flag to “0.”

5 Execute the STP/WIT instruction.

(7) In ordinary operation, if the pulse width of the INT input signal is 2 internal clocks

f ( f(XIN)/2 ) or

more by the built-in noise elimination circuit, it is accepted as an interrupt input. Input the INT input

signal with a pulse width of 100 ns or more in the stop mode and the wait mode.

Reference: As a hardware-level means to prevent incorrect interrupt processing due to noise, a noise

elimination circuit is incorporated in the INT0 and INT1 pins so that no interrupt can be

generated by an “H” pulse (when the rising edge is selected) or an “L” pulse (when a

falling edge is selected) of one machine cycle or less in modes other than the stop mode

and the wait mode. As a software-level means, the levels of the INT0 and INT1 pins are

judged at the beginning of the interrupt processing routine.

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