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AD7156

Rev. 0 | Page 18 of 28

AVERAGE REGISTERS

Ch 1 Address Pointer 0x05, Address Pointer 0x06

Ch 2 Address Pointer 0x07, Address Pointer 0x08

16 Bits, Read Only

Default Value 0x0000

These registers show the average calculated from the previous

CDC data. The 12-bit CDC result corresponds to the 12 MSBs

of the average register.

The settling time of the average can be set by programming

the ThrSettling bits in the setup registers. The average register

is overwritten directly with the CDC output data, that is, the

history is erased if the timeout is enabled and elapses.

FIXED THRESHOLD REGISTERS

Ch 1 Address Pointer 0x09, Address Pointer 0x0A

Ch 2 Address Pointer 0x0C, Address Pointer 0x0D

16 Bits, Read/Write, Factory Preset 0x0886

A constant threshold for the output comparator in the fixed

threshold mode can be set using these registers. The 12-bit

CDC result corresponds to the 12 MSBs of the threshold regis-

ter. The fixed threshold registers share the address pointer and

location on chip with the sensitivity and timeout registers. The

fixed threshold registers are not accessible in the adaptive thre-

shold mode.

SENSITIVITY REGISTERS

Ch 1 Address Pointer 0x09

Ch 2 Address Pointer 0x0C

8 Bits, Read/Write, Factory Preset 0x08

Sensitivity registers set the distance of the positive threshold above

the data average, and the distance of the negative threshold below

the data average, in the adaptive threshold mode.

NEGATIVE

THRESHOLD

POSITIVE

THRESHOLD

DATA AVERAGE

OUTPUT ACTIVE

TIME

SENSITIVITY

DATA

SENSITIVITY

Figure 37. Threshold Sensitivity

The sensitivity is an 8-bit value and is mapped to the lower eight

bits of the 12-bit CDC data, that is, it corresponds to the 16-bit

data register as shown in Figure 38.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3

SENSITIVITY

BIT 2 BIT 1 BIT 0

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2

12-BIT CDC RESULT

BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2

DATA HIGH

DATA LOW

BIT 1 BIT 0

Figure 38. Relation Between Sensitivity Register and CDC Data Register

For an ideal part with no gain error, the sensitivity can be

calculated using the following equation:

)

(pF

2560

)

(

Range

Input

Reg

Sens

Sensitivit

Or the same equation with hexadecimal numbers

)

(pF

)

(

Range

Input

Reg

Sens

Sensitivit

With gain error included, the sensitivity can be calculated using

the following equation:

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

100

(%)

)

(

2560

)

(

Error

Gain

Range

Input

Reg

Sense

Sensitivit

Or the same equation with hexadecimal numbers

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

100

(%)

)

(

)

(

Error

Gain

Range

Input

Reg

Sense

Sensitivit

TIMEOUT REGISTERS

Ch 1 Address Pointer 0x0A

Ch 2 Address Pointer 0x0D

8 Bits, Read/Write, Factory Preset 0x86

Table 9. Timeout Register Bit Map

Bit

Mnemonic

Default

[7:4]

TimeOutApr

0x08

[3:0]

TimeOutRec

0x06

These registers set timeouts for the adaptive threshold mode.

The approaching timeout starts when the CDC data crosses the

data average ± sensitivity band toward the threshold, according

to the selected positive, negative, or window threshold mode.

The approaching timeout elapses after the number of conversion

cycles equals 2TimeOutApr, where TimeOutApr is the value of the

four most significant bits of the timeout register.

The receding timeout starts when the CDC data crosses

the data average ± sensitivity band away from the threshold,

according to the selected positive or negative threshold mode.

The receding timeout is not used in the window threshold

mode. The receding timeout elapses after the number of

conversion cycles equals 2TimeOutRec, where TimeOutRec is the

value of the four least significant bits of the timeout register.

When either the approaching or receding timeout elapses (that

is, after the defined number of CDC conversions is counted),

the data average (and thus the thresholds) is forced to follow

the new CDC data value immediately.

When the timeout register equals 0, timeouts are disabled.

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