AD7156 datasheet(3/28 Pages) AD

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AD7156

Rev. 0 | Page 3 of 28

SPECIFICATIONS

VDD = 1.8 V to 3.6 V, GND = 0 V, temperature range = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit1

Test Conditions/Comments

CAPACITIVE INPUT

Conversion Input Range, CIN to EXC2, 3

3.2

4 pF input range

1.6

2 pF input range

0.8

1 pF input range

0.4

0.5

0.5 pF input range

Resolution4, 5

2.0

4 pF input range

1.6

2 pF input range

1.4

1 pF input range

1.0

0.5 pF input range

Maximum Allowed Capacitance, CIN to GND4, 6

See Figure 4, Figure 5, and

Figure 6

Minimum Allowed Resistance, CIN to GND4, 6

MΩ

See Figure 10 and Figure 11

Maximum Allowed Serial Resistance4, 6

kΩ

See Figure 14

Gain Error

−20

+20

Gain Deviation over Temperature4

0.5

%FSR

See Figure 17

Gain Matching Between Ranges4

−2

Offset Error4

CIN and EXC pins disconnected

Offset Deviation over Temperature4

CIN and EXC pins disconnected

See Figure 16

Integral Nonlinearity (INL)4

0.05

Channel-to-Channel Isolation4

Power Supply Rejection4

fF/V

CAPDAC

Full Range

12.5

Resolution (LSB)4

200

Differential Nonlinearity (DNL)4

0.25

LSB

Auto-DAC Increment/Decrement4, 7

% of CIN range

EXCITATION

Voltage4, 7

±VDD/2

Frequency

kHz

See Figure 18

Maximum Allowed Capacitance EXC to GND4, 6

1000

See Figure 7, Figure 8, and

Figure 9

Minimum Allowed Resistance EXC to GND4, 6

MΩ

See Figure 12 and Figure 13

LOGIC OUTPUTS (OUT1, OUT2)

Output Low Voltage (VOL)

0.4

ISINK = −3 mA

Output High Voltage (VOH)

VDD – 0.6

ISOURCE = +3 mA

SERIAL INTERFACE INPUTS (SCL, SDA)

Input High Voltage (VIH)

% of VDD

Input Low Voltage (VIL)

% of VDD

Input Leakage Current

±0.1

±5

μA

Input Pin Capacitance

OPEN-DRAIN OUTPUT (SDA)

Output Low Voltage (VOL)

0.4

ISINK =

−6.0 mA

Output High Leakage Current (IOH)

0.1

μA

VOUT = VDD

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