TMDS261 datasheet(33/42 Pages) TI

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Slave Address

Data

FromReceiver

From Transmitter

A =No Acknowledge(SDA High)

A = Acknowledge

S=StartCondition

P =StopCondition

W=Write

R0007-01

Acknowledge

(FromReceiver)

Start

Condition

Acknowledge

(Receiver)

Acknowledge

(Receiver)

SDA

Stop

Condition

I CDevice Addressand

Read/WriteBit

FirstDataByte

Other

DataBytes

LastDataByte

ACK

R/W

D0 ACK

ACK

T0397-01

Slave Address

Data

Receiver

Transmitter

A =No Acknowledge(SDA High)

A = Acknowledge

S=StartCondition

P =StopCondition

W=Write

R=Read

R0008-01

Start

Condition

SDA

Acknowledge

(FromReceiver)

Acknowledge

(From Transmitter)

Not Acknowledge

(Transmitter)

Stop

Condition

LastDataByte

I CDevice Addressand

Read/WriteBit

FirstData

Byte

Other

DataBytes

ACK

R/W

ACK

T0398-01

Slave Address

TMDS261

www.ti.com............................................................................................................................................................................................ SLLS953 – DECEMBER 2008

During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so

that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the

receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting

device after the last byte is transferred. An example of a write cycle can be found in Figure 42 and Figure 43.

Note that the TMDS261 allows multiple write transfers to occur. See the Example – Writing to the TMDS261

section for more information.

During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its

address. Following this initial acknowledge by the slave, the master device becomes a receiver and

acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from

the slave, the not-acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before

it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 44 and Figure 45.

See the Example – Reading from the TMDS261 section for more information.

Figure 42. I2C Write Cycle

Figure 43. Multiple-Byte Write Transfer

Figure 44. I2C Read Cycle

Figure 45. Multiple-Byte Read Transfer

Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. These resistors should

comply with the I2C specification that ranges from 2 k

Ω to 19 kΩ. When the bus is free, both lines are high. The

address byte is the first byte received following the START condition from the master device. The 7-bit address is

factory preset to 0101 100. Table 7 lists the calls that the TMDS261 responds to.

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TMDS261 Datasheet(PDF) 33 Page - Texas Instruments

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