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PCM1789 Datasheet(PDF) 18 Page - Texas Instruments |
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PCM1789 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 39 page ![]() AUDIO INTERFACE TIMING t LRS 1.4V 1.4V 1.4V BCK (Input) LRCK (Input) DIN (Input) t BCH t BCL t BCY t LRH t DIS t DIH t LRW PCM1789 SBAS451 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com Figure 27 and Table 5 describe the detailed audio interface timing specifications. Figure 27. Audio Interface Timing Diagram for Left-Justified, Right-Justified, I2S, and DSP Data Formats Table 5. Timing Requirements for Figure 27 SYMBOL DESCRIPTION MIN TYP MAX UNIT tBCY BCK cycle time 75 ns tBCH BCK pulse width high 35 ns tBCL BCK pulse width low 35 ns LRCK pulse width high (LJ, RJ and I2S formats) 1/(2 × fS) 1/(2 × fS) sec tLRW LRCK pulse width high (DSP format) tBCY tBCY sec tLRS LRCK setup time to BCK rising edge 10 ns tLRH LRCK hold time to BCK rising edge 10 ns tDIS DIN setup time to BCK rising edge 10 ns tDIH DIN hold time to BCK rising edge 10 ns 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): PCM1789 |
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