TIMING REQUIREMENTS

MS

1.4V

1.4V

1.4V

t

MSH

LSB(D0)

t

MSS

t

MCH

t

MCL

t

MDS

ADR0

MSB(R/ )

W

MC

MD

t

MDH

t

MCY

t

MHH

D7

TWO-WIRE (I

MSB

LSB

1

0

0

1

1

ADR1

ADR0

R/W

PCM1789

Figure 31 shows a detailed timing diagram for the three-wire serial control interface. These timing parameters are

critical for proper control port operation.

Figure 31. Three-Wire Serial Control Interface Timing

Table 11. Timing Requirements for Figure 31

SYMBOL

PARAMETER

MIN

MAX

UNIT

MC pulse cycle time

100

ns

MC low-level time

40

ns

MC high-level time

40

ns

MS high-level time

ns

MS falling edge to MC rising edge

30

ns

MS rising edge from MC rising edge for LSB

15

ns

MD hold time

15

ns

MD setup time

15

ns

The PCM1789 has a 7-bit slave address, as shown in Figure 32. The first five bits are the most significant bits

(MSBs) of the slave address and are factory-preset to '10011'. The next two bits of the address byte are

selectable bits that can be set by MS/ADR0/RSV and ADR5/ADR1/RSV. A maximum of four PCM1789s can be

connected on the same bus at any one time. Each PCM1789 responds when it receives its own slave address.

Figure 32. Slave Address

22

Submit Documentation Feedback

Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): PCM1789