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PCM1789 Datasheet(PDF) 25 Page - Texas Instruments |
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PCM1789 Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 39 page  CONTROL REGISTER DEFINITIONS (SOFTWARE MODE ONLY) PCM1789 www.ti.com.............................................................................................................................................................................................. SBAS451 – OCTOBER 2008 The PCM1789 has many user-programmable functions that are accessed via control registers, and are programmed through the SPI or I2C serial control port. Table 13 shows the available mode control functions along with reset default conditions and associated register addresses. Table 14 lists the register map. Table 13. User-Programmable Mode Control Functions FUNCTION RESET DEFAULT REGISTER(1) LABEL Mode control register reset Normal operation 16 MRST System reset Normal operation 16 SRST Analog mute function control Mute disabled 16 AMUTE[3:0] Sampling mode selection Auto 16 SRDA[1:0] Power-save mode selection Power save 17 PSMDA Audio interface format selection I2S 17 FMTDA[2:0] Operation control Normal operation 18 OPEDA Digital filter roll-off control Sharp roll-off 18 FLT Output phase selection Normal 19 REVDA[2:1] Soft mute control Mute disabled 20 MUTDA[2:1] Zero flag Not detected 21 ZERO[2:1] Digital attenuation mode 0 dB to –63 dB, 0.5-dB step 22 DAMS Digital de-emphasis function control Disabled 22 DEMP[1:0] AMUTEO/ZERO flag selection ZERO2 22 MZSEL ZERO1: left-channel Zero flag function selection 22 AZRO ZERO2: right-channel Zero flag polarity selection High for detection 22 ZREV Digital attenuation level setting 0 dB, no attenuation 24, 25 ATDAx[7:0] (1) If ADR6 or ADR5 is high, the register address must be changed to the number shown + offset; offset is 32, 64 and 96 according to state of ADR6, 5 (01, 10 and 11). Table 14. Register Map ADR[6:0](1) DATA[7:0] DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 16 10 MRST SRST AMUTE3 AMUTE2 AMUTE1 AMUTE0 SRDA1 SRDA0 17 11 PSMDA RSV(2) RSV(2) RSV(2) RSV(2) FMTDA2 FMTDA1 FMTDA0 18 12 RSV(2) RSV(2) RSV(2) OPEDA RSV(2) RSV(2) RSV(2) FLT 19 13 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) REVDA2 REVDA1 20 14 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) MUTDA2 MUTDA1 21 15 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) ZERO2 ZERO1 22 16 DAMS RSV(2) DEMP1 DEMP0 MZSEL RSV(2) AZRO ZREV 23 17 RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) RSV(2) 24 18 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10 25 19 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20 (1) If ADR6 or ADR5 is high, the register address must be changed to the number shown + offset; offset is 32, 64 and 96 according to state of ADR6, 5 (01, 10 and 11). (2) RSV must be set to '0'. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link(s): PCM1789 |
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