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PCM1789 Datasheet(PDF) 24 Page - Texas Instruments

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Part # PCM1789
Description  24-Bit, 192-kHz Sampling, Enhanced Multi-Level ?誇,Stereo, Audio Digital-to-Analog Converter
PDF  39 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCM1789 Datasheet(HTML) 24 Page - Texas Instruments

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TIMING REQUIREMENTS: SCL AND SDA
t
BUF
t
D-SU
t
D-HD
t
SDA-R
t
SDA-F
t
P-SU
t
SCL-F
t
S-HD
t
LOW
t
SCL-R
t
HI
t
S-SU
t
S-HD
START
Repeated
START
STOP
SDA
SCL
PCM1789
SBAS451 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com
A detailed timing diagram for SCL and SDA is shown in Figure 36.
Figure 36. SCL and SDA Control Interface Timing
Table 12. Timing Requirements for Figure 36
STANDARD MODE
FAST MODE
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
fSCL
SCL clock frequency
100
400
kHz
tBUF
Bus free time between STOP and START condition
4.7
1.3
µs
tLOW
Low period of the SCL clock
4.7
1.3
µs
tHI
High period of the SCL clock
4.0
0.6
µs
tS-SU
Setup time for START/Repeated START condition
4.7
0.6
µs
tS-HD
Hold time for START/Repeated START condition
4.0
0.6
µs
tD-SU
Data setup time
250
100
ns
tD-HD
Data hold time
0
3450
0
900
ns
tSCL-R
Rise time of SCL signal
1000
20 + 0.1 CB
300
ns
tSCL-F
Fall time of SCL signal
1000
20 + 0.1 CB
300
ns
tSDA-R
Rise time of SDA signal
1000
20 + 0.1 CB
300
ns
tSDA-F
Fall time of SDA signal
1000
20 + 0.1 CB
300
ns
tP-SU
Setup time for STOP condition
4.0
0.6
µs
tGW
Allowable glitch width
N/A
50
ns
CB
Capacitive load for SDA and SCL line
400
100
pF
Noise margin at high level for each connected device
VNH
0.2 × VDD
0.2 × VDD
V
(including hysteresis)
Noise margin at low level for each connected device
VNL
0.1 × VDD
0.1 × VDD
V
(including hysteresis)
VHYS
Hysteresis of Schmitt trigger input
N/A
0.05 × VDD
V
24
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM1789



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