PACKET PROTOCOL

SDA

SCL

SlaveAddress

R/W

(1)

ACK

(2)

DATA

(3)

ACK

DATA

ACK

1to7

8

9

1to8

9

1to8

9

ACK

9

St

Start

Condition

Sp

Stop

Condition

WRITE OPERATION

Transmitter

DataType

St

M

SlaveAddress

M

W

M

ACK

S

RegAddress

M

ACK

S

WriteData1

M

ACK

S

WriteData2

M

ACK

S

ACK

S

Sp

M

READ OPERATION

Transmitter

M

St

M

SlaveAddress

M

W

S

ACK

M

RegAddress

S

ACK

M

Sr

M

SlaveAddress

(1)

M

R

S

ACK

S

ReadData

M

NACK

M

Sp

DataType

PCM1789

A master device must control the packet protocol, which consists of a start condition, a slave address with the

read/write bit, data if a write operation is required, an acknowledgment if a read operation is required, and a stop

condition. The PCM1789 supports both slave receiver and transmitter functions. Details about DATA for both

write and read operations are described in Figure 33.

(1) R/W: Read operation if '1'; write operation otherwise.

(2) ACK: Acknowledgment of a byte if '0', not Acknowledgment of a byte if '1'.

(3) DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.

The PCM1789 supports a receiver function. A master device can write to any PCM1789 register using single or

multiple accesses. The master sends a PCM1789 slave address with a write bit, a register address, and the

data. If multiple access is required, the address is that of the starting register, followed by the data to be

transferred. When valid data are received, the index register automatically increments by one. When the register

address reaches &h4F, the next value is &h40. When undefined registers are accessed, the PCM1789 does not

send an acknowledgment. Figure 34 illustrates a diagram of the write operation. The register address and write

data are in 8-bit, MSB-first format.

NOTE: M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.

Figure 34. Framework for Write Operation

A master device can read the registers of the PCM1789. The value of the register address is stored in an indirect

index register in advance. The master sends the PCM1789 slave address with a read bit after storing the register

address. Then the PCM1789 transfers the data that the index register points to. Figure 35 shows a diagram of

the read operation.

(1) The slave address after the repeated start condition must be the same as the previous slave address.

NOTE: M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge,

NACK = Not acknowledge, and Sp = Stop condition.

Figure 35. Framework for Read Operation

Copyright © 2008, Texas Instruments Incorporated

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