PCA9701_PCA9702_3

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 — 3 December 2008

6 of 28

NXP Semiconductors

PCA9701; PCA9702

18 V tolerant SPI 16-bit/8-bit GPI with INT

7.

Functional description

PCA9701 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output

designed to monitor switch status. By putting an external 100 k

Ω series resistor at the

input port, the device allows the input to tolerate momentary double 12 V battery, reverse

battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted

when an input port status changes. The open-drain interrupt output is enabled when

INT_EN is HIGH and disabled when INT_EN is LOW. The input port status is accessed

via the 4-wire SPI interface. The PCA9702 is the 8-bit version of the PCA9701.

Multiple PCA9701 or PCA9702 devices can be serially connected for monitoring a large

number of switches by connecting the SDOUT of one device to the SDIN of the next

device. SCLK and CS must be common among all devices and interrupt outputs may be

tied together. No external logic is necessary because all the devices’ interrupt outputs are

open-drain that function as ‘wired-AND’ and can simply be connected together to a single

pull-up resistor.

7.1 SPI bus operation

The PCA9701 or PCA9702 interfaces with the controller via the 4-wire SPI bus that is

comprised of the following signals: chip select (CS), serial clock (SCLK), serial data in

(SDIN), and serial data out (SDOUT). To access the device, the controller asserts CS

LOW, then sends SCLK and SDIN. When reading/writing is complete, the controller

de-asserts CS. See Figure 6 for register access timing.

7.1.1 CS - chip select

The CS pin is the device chip select and is an active LOW input. The falling edge of CS

captures the input port status in the input status register. If the interrupt output is asserted,

the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active.

When CS is HIGH, the SPI interface is disabled.

7.1.2 SCLK - serial clock input

SCLK is the serial clock input to the device. It should be LOW and remain LOW during the

falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel loads

the shift register from the input. The subsequent rising edges on SCLK serially shifts data

out from the shift register. The falling edge of SCLK samples the data on SDIN.

7.1.3 SDIN - serial data input

SDIN is the serial data input port. The data is sampled into the shift register on the falling

edge of SCLK. SDIN is only active when CS is LOW. This input has a 20

µA pull-down

current source.

7.1.4 SDOUT - serial data output

SDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and

switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising

edge of SCLK the most significant bit in the shift register is presented on SDOUT.

Subsequent rising edges of SCLK shift the remaining data from the shift register onto

SDOUT.