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PCA9701 Datasheet(PDF) 9 Page - NXP Semiconductors |
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PCA9701 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 28 page  PCA9701_PCA9702_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 3 December 2008 9 of 28 NXP Semiconductors PCA9701; PCA9702 18 V tolerant SPI 16-bit/8-bit GPI with INT 7.3.1 VIL, VIH and switching points A minimum LOW threshold of 2.0 V is guaranteed for the logical switching points for the inputs. See Figure 7 for details. The VIL is specified as a maximum of 0.40 × VDD and is 2.0 V at 4.5 V VDD. This means that if the user applies 2.0 V or less to the input (with VDD = 4.5 V), or as the voltage passes this threshold, they will always see a LOW. The VIH is specified as a minimum of 0.7 × VDD. This means that if the user applies 3.15 V or more to the input (with VDD = 4.5 V), or as the voltage passes this threshold, they will always see a HIGH. Fig 7. Logic level thresholds for general purpose inputs 002aae128 VI VDD hysteresis minimum 0 V 0.4VDD 0.7VDD HIGH LOW VIH VIL possible ground shift |
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