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PCA9701 Datasheet(PDF) 16 Page - NXP Semiconductors

Part # PCA9701
Description  18 V tolerant SPI 16-bit/8-bit GPI with INT
PDF  28 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9701 Datasheet(HTML) 16 Page - NXP Semiconductors

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PCA9701_PCA9702_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 3 December 2008
16 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
11. Dynamic characteristics
Table 6.
Dynamic characteristics
VDD = 2.5 V to 5.5 V; VSS =0V; Tamb = −40 °C to +125 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock frequency
-
-
5
MHz
tr
rise time
SDOUT; 10 % to 90 % at 5 V
-
35
60
ns
tf
fall time
SDOUT; 90 % to 10 % at 5 V
-
25
50
ns
tWH
pulse width HIGH
SCLK
50
-
-
ns
tWL
pulse width LOW
SCLK
50
-
-
ns
tSPILEAD
SPI enable lead time
CS falling edge to SCLK rising edge
50
-
-
ns
tSPILAG
SPI enable lag time
SCLK falling edge to CS rising edge
50
-
-
ns
tsu(SDIN)
SDIN set-up time
SDIN to SCLK falling edge
20
-
-
ns
th(SDIN)
SDIN hold time
from SCLK falling edge
30
-
-
ns
ten(SDOUT)
SDOUT enable time
from CS LOW to
SDOUT low-impedance; Figure 17
--55
ns
tdis(SDOUT)
SDOUT disable time
from rising edge of CS to SDOUT
high-impedance; Figure 17
--85
ns
tv(SDOUT)
SDOUT valid time
from rising edge of SCLK; Figure 18
--55
ns
tsu(SCLK)
SCLK set-up time
SCLK falling to CS falling
50
-
-
ns
th(SCLK)
SCLK hold time
SCLK rising after CS rising
50
-
-
ns
tPOR
power-on reset pulse time
time before CS is active
after VDD >VPOR
-
-
250
ns
trel(int)
interrupt release time
after CS going LOW; Figure 19
-
-
500
ns
tv(INT_N)
valid time on pin INT
after INn changes or INT_EN
goes HIGH
-
-
100
ns
Fig 14. Timing diagram
CS
SCLK
SDIN
SDOUT
INT
tSPILAG
tWL
tWH
high-impedance
tSPILEAD
MSB in
MSB out
002aac428
tsu(SDIN)
th(SDIN)
ten(SDOUT)
tv(SDOUT)
tdis(SDOUT)
trel(int)
50 %
50 %
tsu(SCLK)
th(SCLK)



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