15

ATF1508ASV(L)

1408H–PLD–7/05

JTAG-BST Overview

The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port

(TAP) controller in the ATF1508ASV(L). The boundary-scan technique involves the

inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each

component so that signals at component boundaries can be controlled and observed

using scan testing principles. Each input pin and I/O pin has its own Boundary-scan Cell

(BSC) in order to support boundary-scan testing. The ATF1508ASV(L) does not cur-

rently include a Test Reset (TRST) input pin because the TAP controller is automatically

reset at power-up. The six JTAG-BST modes supported include: SAMPLE/PRELOAD,

EXTEST, BYPASS and IDCODE. BST on the ATF1508ASV(L) is implemented using

the Boundary-scan Definition Language (BSDL) described in the JTAG specification

(IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be used

to perform BST on the ATF1508ASV(L).

The ATF1508ASV(L) also has the option of using four JTAG-standard I/O pins for in-

system programming (ISP). The ATF1508ASV(L) is programmable through the four

JTAG pins using programming-compatible with the IEEE JTAG Standard 1149.1. Pro-

gramming is performed by using 5V TTL-level programming signals from the JTAG ISP

interface. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not

needed, then the four JTAG control pins are available as I/O pins.

JTAG Boundary-scan

Cell (BSC) Testing

The ATF1508ASV(L) contains up to 96 I/O pins and four input pins, depending on the

device type and package type selected. Each input pin and I/O pin has its own bound-

ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by

IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis-

ters and up to two update registers. There are two types of BSCs, one for input or I/O

pin, and one for the macrocells. The BSCs in the device are chained together through

the (BST) capture registers. Input to the capture register chain is fed in from the TDI pin

while the output is directed to the TDO pin. Capture registers are used to capture active

device data signals, to shift data in and out of the device and to load data into the update

registers. Control signals are generated internally by the JTAG TAP controller. The BSC

configuration for the input and I/O pins and macrocells are shown below.

BSC Configuration Pins and Macrocells (Except JTAG TAP Pins)

Note:

The ATF1508ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as a design option.